A CASE FOR DYNAMIC PIPELINE SCALING (click here for details)
Energy consumption can be reduced by scaling down frequency when peak performance is not needed. A lower frequency permits slower circuits, and hence a lower supply voltage. Energy reduction comes from voltage reduction, a technique called Dynamic Voltage Scaling (DVS). This paper makes the case that the useful frequency range of DVS is limited because there is a lower bound on voltage. Lowering frequency permits voltage reduction until the lowest voltage is reached. Beyond that point, lowering frequency further does not save energy because voltage is constant. However, there is still opportunity for energy reduction outside the influence of DVS. If frequency is lowered enough, pairs of pipeline stages can be merged to form a shallower pipeline. The shallow pipeline has better instructions-per-cycle (IPC) than the deep pipeline. Since energy also depends on IPC, energy is reduced for a given frequency. Accordingly, we propose Dynamic Pipeline Scaling (DPS). A DPS-enabled deep pipeline can merge adjacent pairs of stages by making the intermediate latches transparent and disabling corresponding feedback paths. Thus, a DPS-enabled pipeline has a deep mode for higher frequencies within the influence of DVS, and a shallow mode for lower frequencies. Shallow mode extends the frequency range for which energy reduction is possible. For frequencies outside the influence of DVS, a DPS-enabled deep pipeline consumes from 23% to 40% less energy than a rigid deep pipeline.

DESIGN AND IMPLEMENTATION OF 4 BIT SLICE MICROPROCESSOR (AMD 2901) USING CMOS TECHNOLOGY (NOVEMBER 2001, NCSU)
This project involves design of the microprocessor AMD2901 and implement using the VLSI technology. The entire chip was designed using the CMOS TSMC 0.35µ technology. Then the layout of the chip was made.

DESIGN AND SIMULATION OF DYNAMIC BRANCH SCHEDULER USING TOMASULO'S ALGORITHM (NOVEMBER 2001, NCSU)
This project involves the simulation of Dynamic Branch Schedulers commonly available in all the computers. The algorithm used was Tomasulo's Algorithm. The dynamic branch scheduling (i.e. hardware scheduling) helps in super scalar processing of the computer thereby increasing its speed.

DESIGN AND SIMULATION OF BIMODAL, G-SHARE, AND HYBRID BRANCH PREDICTOR WITH SELECT AND GLOBAL BRANCH HISTORY (OCTOBER 2001, NCSU)
This project involves the simulation of Branch Predictors. The branch predictors are very useful in hardware of computer as they increase the processing speed of the computer. There are lot of branches and loops in the instructions and they cause CONTROL HAZARDS. They are taken care of by branch predictors.

DESIGN AND SIMULATION OF N-WAY SET ASSOCIATIVE CACHE FOR UNI-PROCESSOR SYSTEM (SEPTEMBER 2001, NCSU)
This project involves the simulation of N-way set Associative caches. Caches help a lot to simulate a faster memory. The performance with and without Victim Cache is also studied and the same is designed.

SIMULATION, DESIGN AND IMPLEMENTATION OF THE TRELLIS CODEC (CONVOLUTIONAL ENCODER AND VITERBI DECODER)
Location: Space Application Centre, Indian Space Research Organization, Ahmedabad
Duration: June 2000 to May 2001
This project involves simulation of the entire Digital Communication System. The data is encoded using rate 1/3 and ˝ convolutional code, modulated using BPSK/QPSK modulation, sent through a BSC channel characterized by AWGN noise and Rayleigh Fading, demodulated (hard and soft) and then decoded using Viterbi Algorithm (both for hard and soft values) or SOVA. The performance charts were charted for uncoded and coded data. The project is going to be later expanded to 16PS.
The simulation was done on MATLAB (static). The bit error rate was typically 10^-3 to 10^-6. The system was then implemented in hardware through ALTERA MAX+PLUSII VHDL language. The chips used were MAX EPM7128SLC-10 and EPM7064LC - 10. The system was tested in real time. The decoder is asynchronous and uses unique word detection technique. The rate ˝ decoder has been proposed for use in GSAT-II.

BLOCK TURBO ENCODER/DECODER - SIMULATION AND IMPLEMENTATION 
Location: Space Application Centre, Indian Space Research organization, Ahmedabad
Duration: June 2000 to May 2001
This is an extension to the earlier project. The codes have been transformed into much powerful turbo codes. This is then turbo decoded using iterative techniques and Log likelihood algebra. Once again the system was simulated in MATLAB, with ASK modulation and decoded (soft) using iterative techniques. This was again implemented through VHDL language ALTERA MAX+PLUSII and tested in real time.

ADVANCED PICTURE CODING (click here for details) 
Picture in its very basic form is made up of still images and a series of still images. Using a digital computer for processing of analog video signals needs conversion of the picture into individual pixels. A digital video data consists of 480 lines each of 640 pixels. Thirty such frames of raw video amounts to about 9.2MB of data. This shows that video information storage in a computer eats up a lot of storage space. A solution to this problem is compression. There are number of ways of compression and decompression known as advanced methods of picture coding. A few well know standards are H.261 (video codec or P*64 compression method), JPEG, MPEG, TIFF, GIF and others. Compression is an important phenomenon required for bandwidth-hungry multimedia applications especially on Internets and Intranets and it is a growing field of research for the software industry.

POWER ELECTRONICS AND DRIVES (click here for details) 
Power electronics seemed for a long period an obsolete area with very few innovations. This period of stagnation is replaced now due to rapid developments in semiconductor technology. This development boosts development in all areas of power electronics, too: the power semiconductors, the topologies of converters and inverters, the control strategies and furthermore modern computer-aided-design and optimization-tools. This paper will discuss the different aspects. With thyristor, power converters achieving popularity in the area of adjustable speed drives, the operational problems of motors on these converters have started posing problems. The huge losses during operations of the motor, has led to various design of inverters and converters and thyristors have replaced transistors in PWM techniques. Nowadays microcontrollers are replacing analog controllers, which minimizes losses due to component drift and temperature. This has made implementation of sophisticated drives and its monitoring possible. Motor drives are used in applications ranging from very precise, high-performance position-controlled drives in robotics to variable-speed drives. In all such drives, a power electronic converter is needed as an interface between the input power and the motor. Power electronics is regarded by many people as a classical subject, where few, if any, innovations take place. It has been the aim of this paper to show that in the last ten years a remarkable development has started. All these developments are in full progress now. So many challenging problems are waiting for the engineers in the future.