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M.S. in Electrical Engineering (Specialized in Computer Architecture, VLSI, ASIC and Circuit Design)
B.E. in Electronics and Communications (Specialized in Electronics, Digital Communications and DSP)
This is more serious stuff......
I have included some of my projects for download... Click here
Some of the programs in "C" are for download... Click here
I have even helped my college department in developing "Analog Circuit Application (ACA)" and the "TV lab" by designing the "Voltage Shunt Feedback Amplifier" and the "EHT and Horizontal Amplifier Section" respectively.
I have also helped as lab instructor for "C".
My other projects include "Guitar Headphone Amplifier" and "PC interface multimeter through serial port". I have been an active participant in IEEE activities, organizing and delivering lectures such as on "Fundamentals of Electronics" and "Pulse Electronics".
My recent Projects...
There are number of files in a single project, so I have zipped all the files in respective projects
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N-way Set Associative Cache - This project and the two more projects that follow were a part of my Master's Curriculum. The objective of this project is to simulate the real time processing L1 cache. The simulator has a option to work with/without Victim Cache (which is not like L2 cache). Refer Computer Architecture: A Quantitative Approach by Hannessey and Patterson for more description. The simulator can also choose between two write policies: WTNA (Write through No Allocate) and WBWA (Write back with allocate). The performance with each of the write policies is studied. Various trace files are used (for eg. Gcc, compress, perl) for running this simulator. Because of size considerations I cannot include these trace files but some result files are included. You can generate your own trace file.
Cache.h: This is a header file for the simulation functions for cache
Dmcache.c: This is the main C file where the simulator runs
Result.txt: Sample cache run
Compress.xls: sample design run for compress trace for WTNA policy
(These 4 files are available as cache.zip)
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Bimodal,
G-Share and Hybrid Branch Predictor with
select and Global Branch History - The
objective of this project is to simulate the
hardware branch predictors used in computers
to improve the performance when there are a
lot of loops. The main aim of branch predictor
is to predict the path of branch and reduce
hardware misses to improve the speed of
performance. Various branch predictors are
studied here. Here also a trace file is used.
Branch.h:
The header file containing all the simulator
functions
Predictor.c: The main C file where the
simulator runs
Result.txt: Sample branch predictor run
Description: Design Description and comparison
of various trace files
Design Space search (Design.doc): The
extension to above file.Shows various design
search description
Hybrid.xls: Design of the branch predictor for
optimal performance for specified benchmarks
(These files are available as predictor.zip) |
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Dynamic Branch Scheduler using Tomasulo's Algorithm - This is one of the best projects. It involves super scalar performance of a computer. The super scalar performance is achieved using Tomasulo's Alogrithm. The instructions are fetched in multiple numbers. They are checked for dependencies and the registers are renamed (This is a beautiful concept which removes anti dependencies). Then they are dispatched according to available bandwidth or direct dependencies. This project can also be implemented using a ROB (re-order buffer).
Tomasulo.h: The header file containing all simulator functions
scheduler.c: The main C file
ipc.txt: The result file showing the superscalar results of the simulator
result.txt: The result file seems kind of weird. The result file is input to a scope tool which produces the pipelined output
scope.txt: The first ten and last ten instructions in a pipelined format
Graphs.xls: The various plots showing IPC (instructions per count) vs. Scheduler Size
Discussion.doc: Discussion of the shape of various graphs.
(These files are available as tomasulo.zip) |
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These are the Projects in "C"...
The "C" files are in ZIP format... unzip them and then run in "C"
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Anidemo1.C - A ball ricocheting along the sides of the computer screen |
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Password.C - A password program |
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Mandel.C - Arrangement of mandel brot |
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Graphic Input demo.C - An example taking input in graphical format |
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Dance.C - Distortion of DOS screen, appears it is dancing |
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DiskInfo.C - Program informing about the data space, number of clusters, sectors/clusters, bytes/clusters |
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ShowTime.C - A program which shows the current system time & the DOS time |
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CyberProbe.C - A game of arranging balls in two circular rings. If anyone has any algorithm of solving this game, do contact me |
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Control.C - A program showing the current status of scroll lock, num lock, caps lock, insert, ctrl, alt, left shift and right shift |
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Gmouse.H (Header file) - A header file showing the functions and data types used for mouse interfacing |
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MouseDemo.C - A demonstration of mouse on the screen |
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Admission.C - A front end admission process software. I am too lazy to write the database of this program (very boring). You can use a simple link list and add to the program |
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Sameer.C - A demonstration of graphic animation. Shows a lot of flicker. A tedious way is there to reduce the flicker, but you can enjoy this |
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Some more programs...
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RS232.C - This program enables communication between 2 PCs using RS232 serial port. This program is incomplete and I invite you to complete it |
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Tout.C - Transmitting module of RS232 serial communication |
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Rinp.C - Receiving module of RS232 serial communication |
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ShortP.C - This program uses DJAKSTRA as algorithm to compute short S path between 2 nodes on the network. This is the routing algorithm used in network layer |
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Time_si.C - This program simulates the switching mechanism used in network communications, specifically time slot interchange |
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